1. Field of the Invention
The present invention generally relates to a semiconductor process. More particularly, the present invention relates to a method of fabricating gates.
2. Description of Related Art
In a conventional MOS process, a gate dielectric layer and a poly-Si layer are sequentially formed on a substrate, and then the poly-Si layer is patterned into a gate using lithography and etching techniques. Thereafter, ion implantation is conducted to form a source/drain region in the substrate beside the gate.
The conventional material of MOS gates is doped poly-Si. However, poly-Si is not an ideal gate material in advanced processes for having higher resistance. Therefore, metal is currently used to form the gates in many advanced MOS processes to solve the above problem.
Unfortunately, a metal gate has a disadvantage that defects are easily produced at the interface between the metal gate and the gate dielectric layer during the etching process of the metal gate. In addition, when devices become smaller, exactly defining a metal gate through metal etching is more difficult.
On the other hand, the integration of metal-gate CMOS process including PMOS and NMOS processes suffers from many problems, such as etching, thermal or contamination issue. Especially, it is hard for NMOS and PMOS devices to maintain their optimal wok functions. Therefore, the performance of the CMOS device cannot be well adjusted.